1. Field of the Invention
The invention generally relates to testing of semiconductor devices, and more particularly to testing of integrated circuits which include multiple cores.
2. Description of the Related Art
The manufacturing of integrated circuits includes testing of the circuits to ensure their proper operation and to gain information about possible failures. Integrated circuits of low complexity may be tested using functional tests, for which test patterns or test vectors may be applied to the integrated circuit (also referred to as “chip”) by an automated test equipment (ATE), wherein the test patterns may be developed to prove the complete functionality of this integrated circuit. However, for integrated circuits with high complexity, it may be more efficient to test each block of the chip separately rather than testing the complete chip as a whole. In this case, the ATE may provide dedicated test patterns for each structural block that is to be tested within the integrated circuit. The resulting output is in turn captured by the ATE where it is analyzed.
FIG. 1 illustrates an example for an integrated circuit chip to be tested. Chip 100 comprises a core 130, which may include random logic such as a processor core. Furthermore, chip 100 includes one test input 110, which may be an n-bit port at which an ATE can apply an n-bit test vector, thereby supplying the n-bit test vector to the core 130 via an n-bit bus. Furthermore, the chip 100 includes a test output 120, which may be an n-bit port that is connected to the core 130 over an n-bit bus, thereby enabling the ATE to capture output data of the core 130 that result when operating the core 130 with the test input data.
Due to the ongoing advancements in shrinking the feature sizes of semiconductor devices and the resulting increase in chip complexity, the semiconductor industry tries to manufacture integrated circuit chips which integrate several components of a system which were previously manufactured as separate semiconductor chips. For example, one semiconductor chip may include several processor cores which are substantially identical, thereby resulting in a single-chip multiprocessor.
Testing such multicore chips in the conventional manner shown in FIG. 2 would result in a substantial increase of test time and required Input/Output pins. Therefore, the issue arises of how to efficiently test the circuitry of integrated circuits which have a plurality of substantially similar cores.